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The semiconductor industry has been running the same race for over half a century, a marathon governed by the gospel of Moore’s Law. The objective was always clear: make transistors smaller, pack more of them onto a silicon wafer, and reap the rewards of faster, more powerful, and more efficient processors. But the finish line of that race is now agonizingly in sight. As we venture into the atomic-scale frontiers of 3-nanometer and 2-nanometer process nodes, the costs have become astronomical, and the physical gains have dwindled to a trickle. The engine of innovation is sputtering.

From this looming crisis, a new philosophy is emerging. What if the answer isn’t smaller components, but smarter design? This is the question at the heart of NeoLogic, a nimble Israeli startup founded in 2021 that is making a bold claim: they can slash the power consumption of a processor by half and its physical size by 40%, all without reinventing the multi-trillion-dollar manufacturing infrastructure the world relies on. Armed with a fresh $10 million in Series A funding, the company is preparing to introduce its “CMOS+” technology to the world, targeting the most power-hungry and critical sector of modern computing: the AI data center, with a planned debut in 2026.

The Hidden Traffic Jam Inside Every Chip

To understand the quiet revolution NeoLogic is proposing, one must first grasp a fundamental, yet often overlooked, limitation in conventional chip design. Modern processors are built using a technology called CMOS (Complementary Metal-Oxide-Semiconductor), a robust and reliable standard for decades. Within this standard, the basic building blocks of computation are “logic gates”—microscopic switches that perform simple operations like AND, OR, and NOT.

The problem lies in something called “fan-in,” which is simply the number of inputs a single logic gate can handle. For standard CMOS gates, this number is incredibly small, typically capped at four. Imagine trying to build a complex highway system where every exit ramp can only have four lanes. What happens when you need to manage traffic from eight, sixteen, or even thirty-two different sources?

The current solution is brute force. Chip designers are forced to construct enormous, sprawling “tree structures” of interconnected gates. To handle a 16-input signal, for instance, they must first feed it into four separate 4-input gates, then take the outputs of those gates and feed them into another gate, and so on. This multi-stage process creates a digital Rube Goldberg machine inside the processor. It works, but it’s wildly inefficient. These trees consume a vast amount of physical space on the chip, they leak power with every calculation, and they introduce delays, lengthening the “critical path”—the longest time it takes for a signal to travel through the circuit, which ultimately limits the processor’s clock speed.

NeoLogic’s Solution: A Digital Superhighway

NeoLogic’s CMOS+ technology doesn’t just try to optimize the old, inefficient road network; it tears it up and builds a superhighway in its place. The company has developed a new way to design logic gates that shatters the traditional fan-in limit.

A Fundamental Leap in Gate Capability

Instead of being restricted to four inputs, CMOS+ enables the creation of single-stage logic gates that can handle anywhere from 6 to 32 inputs simultaneously. In our highway analogy, this is the equivalent of replacing a convoluted network of interchanges and off-ramps with a single, massive, 32-lane exit that directs traffic exactly where it needs to go in one clean step. By eliminating the need for complex tree structures, NeoLogic claims it can reduce the number of transistors required for a given function by as much as three times.

This isn’t just a theoretical improvement; it has profound, cascading effects on the entire chip. With fewer transistors and a more direct signal path, the two most precious resources in chip design—area and power—are dramatically conserved. The company’s projections are striking: up to a 50 percent reduction in power consumption and up to a 40 percent reduction in the required chip area (die size), all while maintaining comparable latency to existing designs.

A Full Toolkit for the Modern Chip Architect

The innovation doesn’t stop at logic gates. NeoLogic understands that a modern processor is a complex ecosystem of different components. Their CMOS+ technology also extends to other critical elements, offering highly power-efficient registers, buffers, and arithmetic blocks. This provides chip designers with a complete, cohesive toolkit to build processors from the ground up with efficiency as the guiding principle. It’s a holistic rethinking of the processor’s internal architecture, allowing for far more elegant and streamlined designs that achieve a new balance between power, performance, and area.

The Economic Imperative in an Age of Staggering Costs

The technical elegance of CMOS+ is compelling, but its true disruptive potential lies in its economic implications. The semiconductor industry is grappling with a severe cost crisis at the leading edge, and NeoLogic’s approach offers a powerful financial antidote.

Breaking Free from the Tyranny of the Nanometer

For years, the industry benefited from Dennard scaling, a principle that ran parallel to Moore’s Law, stating that as transistors shrank, their power density remained constant. This meant smaller transistors were also more energy-efficient. That principle broke down over a decade ago. Now, shrinking transistors offers diminishing returns on power and performance, while the cost of manufacturing them has gone hyperbolic.

The price tag for building a new fabrication plant (a “fab”) capable of producing 3-nanometer or 2-nanometer chips now exceeds $20 billion. The cost of a single silicon wafer at these advanced nodes can run into the tens of thousands of dollars. Compounding this, the microscopic complexity leads to lower yields, meaning a higher percentage of the chips on each wafer are defective and must be discarded. This is a game that only a handful of mega-corporations can afford to play.

NeoLogic’s value proposition directly attacks this economic bottleneck. By reducing the die area by up to 40%, it allows a manufacturer to fit significantly more chips onto a single, expensive wafer. This immediately increases the output per wafer and improves the effective yield, drastically lowering the cost per functional chip. It offers a path to cost-effective high-performance computing without needing to bet the entire company on the next, even more expensive, process node.

The Plug-and-Play Revolution

Perhaps the most brilliant aspect of NeoLogic’s strategy is its commitment to compatibility. The company isn’t asking the industry to abandon its decades of investment and expertise.

No New Fabs Required

CMOS+ is designed to be fully compatible with existing CMOS manufacturing processes. A chip designed with NeoLogic’s principles can be fabricated in any existing fab, from older, mature 130nm nodes to the cutting-edge 2nm nodes currently in development. This eliminates the single greatest barrier to adoption for any new hardware technology: the need for new, specialized, and prohibitively expensive manufacturing infrastructure.

Leveraging the Existing Ecosystem

Furthermore, the technology integrates seamlessly with the standard Electronic Design Automation (EDA) tools from companies like Synopsys, Cadence, and Siemens. These are the software platforms that virtually every chip engineer in the world uses to design, simulate, and verify processors. By working within this established ecosystem, NeoLogic ensures that engineers don’t need to be retrained and design workflows don’t need to be upended. It transforms a potentially radical, disruptive technology into what feels like a powerful, drop-in upgrade.

Targeting the Power-Hungry Heart of Modern Computing

While the benefits of CMOS+ could eventually find their way into everything from smartphones to automobiles, NeoLogic has set its initial sights on the most demanding and fastest-growing segment of the market: the artificial intelligence data center.

Taming AI’s Voracious Appetite for Energy

The AI revolution, powered by large language models and deep learning, is creating an unprecedented energy crisis. According to some estimates, the world’s data centers already consume between 1-2% of global electricity, and the explosive growth of AI is projected to increase that demand exponentially. Some projections suggest that by 2030, the information and communication technology sector could account for over 20% of global electricity demand, with AI being the primary driver. This level of consumption is not only economically costly but also environmentally unsustainable.

NeoLogic’s promise of a 50% reduction in processor power is therefore not just an incremental improvement; it’s a potential lifeline. For a hyperscale data center operator like Google, Amazon, or Microsoft, a 50% power cut at the chip level translates into billions of dollars in saved electricity costs, reduced cooling requirements, and a significantly smaller carbon footprint. It could enable the training and deployment of next-generation AI models that are currently considered too power-intensive to be practical.

This strategic focus is what attracted investors like KOMPAS VC, which led the $10 million funding round. “We are backing NeoLogic as they push the boundaries of computing with their breakthrough approach to energy-efficient processors,” said Talia Rafaeli, a Partner at the firm. “The team’s deep technical expertise and innovative CMOS+ technology position them to impact the AI data center space significantly.” Her statement underscores the market’s urgent need for exactly what NeoLogic is offering: a smarter path to performance that doesn’t rely on brute-force energy consumption.

With customer demonstrations already underway, the company is on a clear path toward its 2026 goal of seeing its technology deployed in live data center environments. If NeoLogic succeeds, it won’t just be a victory for one startup. It will signal a pivotal paradigm shift for the entire semiconductor industry—a move away from the simple, physical pursuit of “smaller” and toward a more sophisticated, architectural pursuit of “smarter.” In an era where the old rules of computing are breaking down, NeoLogic is betting that the future belongs to those who are bold enough to write new ones.

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Source: https://www.techradar.com